1. Field
The following description relates to a technique for processing a nested loop, and additionally, to a technique for processing a nested loop by allocating commands included in a nested loop to a plurality of processing elements and processing the allocated commands.
2. Description of the Related Art
Reconfigurable architecture refers to architecture in which a hardware configuration of a computing apparatus may be changed to more efficiently process a given task.
In processing a task in a hardware manner, even a slight change in the task may not be efficiently dealt with because hardware functions are rigid. In contrast, in processing a task in a software manner, software can be more easily optimized to the task, but the processing speed is slower than processing in a hardware manner.
Reconfigurable architecture has the advantages of both hardware/software processing. For example, reconfigurable architecture has drawn significant attention from a digital signal processing field in which the same process is recursively executed.
In general, a digital signal processing procedure includes multiple loop operations that repeat the same task. To increase loop operation speed, loop level parallelism (LLP) may be used. A representative example of LLP is software pipelining.
Typically, an inner loop and an outer loop which are included in a nested loop are processed in series in reconfigurable architecture. However, the series processing may substantially lengthen the processing time of the loop operation.